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Problems With SDRAM

Who generated the timing register values for the old revision? Now that you've read that, do you feel a bit confused about exactly what type of SDRAM you need? SDRAMInit(); wr_ptr = (uint32_t *)SDRAM_BASE_ADDR; char_wr_ptr = (uint8_t *)wr_ptr; /* Clear content before 8 bit access test */ _DBG_("Clear content of SDRAM..."); for ( i= 0; i < SDRAM_SIZE/4; i++ ) Switching the chip for a 1GB DDR3 that I had in a laptop worked perfectly. this contact form

the memory is 16 bits wide, so A31..A1 addresses memory words, depending on the memory size with collumn address length of 9, 4 banks, row lenbgth of 12 that uses the Why do researchers use extremely complicated English sentences to convey their meaning? The error occurs when A22 is high. Log in or register to post comments Top t0mmy Level: Rookie Joined: Thu.

Message 2 of 3 (4,773 Views) Everyone's Tags: DDR3memorymigML605 View All (4) Reply 0 Kudos shawayek Observer Posts: 29 Registered: ‎12-13-2013 Re: DDR3 SDRAM tests failing, strange memory problems Options Mark LPC11U24 Active Mode Supply Current I2C EEPROM Problem LPCOpen2.12 sdmmc / massstorage performance bug No initialize flash array Problem on LPC2148 I2C Is there something missing from Chapter 6 of UM10524 Please consider a donation to The PC Guide Tip Jar. First Photo Shows Successfull Read Write: Second photo shows Faulty Datas: And interesting one is Third Photo.

  • Just to confirm, it is like drop and replacement ?
  • The current trend appears to be toward 4-clock SDRAMs.
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  • regards Phil.
  • for BRC BS = A23..A22, row address = A21..A10, collum Address = A9..A1 for RBC row address = A23..A12, BS = A11..A10, collum Address = A9..A1 The fact that both Row
  • Thomas Top Tue, 2012-06-12 09:59 #9 PhilYoung Offline Joined: 2011-07-18 Posts: 80 Hi Thomas.

Here is your PCB layout with most impedance change highlighted, on some lines there is way to much impedance changes. In fact, the term is a misnomer; the "2" and "3" refer to the latency of the CAS line, so the terms should be "CL2" and "CL3". Hope this helps regards Phil. And maybe a logic analyzer to check the validity of your timings.

Using CAS 3 133 MHz is possible Address Connections LPC SDRAM A0 A0 A1 A0 .. .. .. .. The presentation also delves into such issues as the tools that you will need to perform DDR validation, as well as finding and maintaining the data eye. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff. © Copyright 1995-2016 Texas Instruments Incorporated. Could you send recommended configuration for interfacing withMT48LC16M16A2TG-7E:G Prodigy 70 points Alexey Shatrov Oct 15, 2014 8:44 AM Reply Cancel Cancel Reply Suggest as Answer Use rich formatting 8 Replies

Content on this site may contain or be subject to specific guidelines or limitations on use. No, you _have_ to use A13 and A14 as bank select, regardless of the number of address lines the SDRAM has. Basics: I'm using a LPC1788 at 120 MHz and the EMC clk is set to 120 MHz as well. bye, Ole Reinhardt Top Tue, 2012-06-05 02:47 #4 tjoAG Offline Joined: 2012-05-30 Posts: 50 Hi Well, it seems I have got it to work now.

Maybe I just need to change some timing parameters, I don't know. Trademarks | Privacy Policy | Terms of Use Home Blogs Forums Projects Downloads FAQ Global/English Languages: Global 简体中文 NOTICE:This website will be shut down in the near future. more stack exchange communities company blog Stack Exchange Inbox Reputation and Badges sign up log in tour help Tour Start here for a quick overview of the site Help Center Detailed I am not in a position to do this evaluation for them.

In practice, you really want memory rated slightly higher than what is required, so 10 ns modules are really intended for 83 MHz operation. 100 MHz systems require faster memory, which http://olivettipc.com/problems-with/problems-with-ie-6.html To do this we usually put a GND plane under traces and adjust the vertical distance to have the right impedance. But yes it is a poor returning path. Home Categories FAQ/Guidelines Terms of Service Privacy Policy Powered by Discourse, best viewed with JavaScript enabled TI E2E Community Menu Search through millions of questions and answers User Menu Search through

Also note that the EMC of the LPC1788 is only rated to 80MHz not 120MHz and the EMC clock is feed from the CPU clock not the MUX as shown in Sep 25, 2008 Posts: 21 View posts Location: Germany #6 Posted by t0mmy: Tue. Was this done by the customer or copied from an existing EVM or reference design from TI? http://olivettipc.com/problems-with/problems-with-hjt.html This company sponsors the NetSeminar series and its Internet seminar on DDR, entitled, "The Challenge of DDR PC266 and Beyond: Design and Validation of High-Speed Memory Buses." Perry Keller, senior engineer

Do I have a faulty memory chip? the address bus from the CPU is a byte address bus, so for 32 bit accesses the word address is A31..A2, for 16 bit it's A31..A1, and A31..A0 for 8 bits. The customer, or you, will want to go through every timing parameter and make sure that the old settings were correct.

Please use the latest processor SDK package for your platform (K2H,K2E,C665x,C667x etc.,) http://www.ti.com/lsds/ti/tools-software/processor_sw.page Reply Cancel Cancel Reply Suggest as Answer Use rich formatting TI E2E™ Community Support Forums Blogs Videos Groups

What is the opposite of Cancel? The SDRAM i use has a CAS latency of 3 with clocks <= 133Mhz and 2 with clocks < 100 MHz I just use CAS 3 to be sure, I can The problem here is: it seems as the _init_startup function is not executed. Regards, Titus S.

As you may have read, I got my sdram running fine. NOTE: Using robot software to mass-download the site degrades the server and is prohibited. Log in or register to post comments Top t0mmy Level: Rookie Joined: Thu. his comment is here So just to be sure: Not setting MODE register in the SDRAM requires to use the CPU A13 and A14 as bank select Setting MODE register in the SDRAM, "any" address

SDRAM accomplishes its faster access using a number of internal performance improvements, including internal interleaving, which allows half the module to begin an access while the other half is finishing one. But when i tried to Access bunch of a place on SDRam, Data corrupts. Regards,RandyP Search for answers, Aska question, click Verify when complete, Helpothers, Learn more. You need to make sure that you get the right kind for your motherboard.

But here, if I enable the LCD controller the data in the SDRAM is corrupted??? is error in data bus or in address bus. This means that when your CPU is running at 120MHz the max your EMC can run at is 60MHz (CPU/2) MAC Top Thu, 2016-02-18 06:12 #14 Prabhakaran_Raja Offline Joined: 2015-10-08 Posts: Thank you!

I suspect that the main problem is earth plane problems. Sep 25, 2008 Posts: 21 View posts Location: Germany #3 Posted by t0mmy: Mon. With SDRAM however, the whole point of the technology is to be able to run with zero wait states. But again, something state otherwise I have lowered the EMC clock to 60MHz to be a bit larger with the timing.

For example, the reciprocal of 10 ns is 100 MHz, so people assume that 10 ns modules will definitely be able to run on a 100 MHz system. Micron SDR SDRAM devices built with the 130nm process have been available and in use for many years. From the Appnote I was under the impression that you want to init SDRAM before main in order to support data and bss in SDRAM. Before this is not solved, I can't go ahead.

http://www.micron.com/parts/dram/sdram/mt48lc16m16a2tg-7e Reply Cancel Cancel Reply Suggest as Answer Use rich formatting Guru 116110 points Titusrathinaraj Stalin Oct 15, 2014 2:14 PM In reply to Alexey Shatrov: Hi Alexey, If Check the SDRAM specs for the skew tolerance. I now have my SDRAM working as expected If you ever come to DK I will give you free Beer I also have tried running at 120 MHz EMC clock. Top Thu, 2012-06-14 21:32 #12 tjoAG Offline Joined: 2012-05-30 Posts: 50 Hi Phil Thanks a lot for you help.

i using LPCXpresso v7.9.2 IDE.